以Verilog 設計一個數位電路 (EX1-1)--- 74LS139

以Verilog 設計一個數位電路 (EX1-1)--- 74LS139

`timescale 1 ns/1 ns

module ex1_74LS139 (A, B, G, Y);
input A,B,G;
output [3:0]Y;


assign Y[0]= ~G & (~A & ~B);
assign Y[1]= ~G & (~A &  B);
assign Y[2]= ~G & ( A & ~B);
assign Y[3]= ~G & ( A &  B);

endmodule

`timescale 100 ns/1 ns

module TB;

reg A,B,G;

wire [3:0]Y;

integer i;

ex1_74LS139 UUT (A, B, G, Y);

initial 

begin

for (i=0;i<=7;i=i+1) begin

{G,A,B}=i;

#20;

end

#20;

$stop;

end

endmodule