以Verilog 設計一個數位電路 (EX1-4)--- 74LS155

以Verilog 設計一個數位電路 (EX1-4)--- 74LS155

`timescale 1 ns/1 ns
module ex4_74LS155 (A, B,C1,G1,C2,G2 ,Y1 , Y2);
input A,B,C1,C2,G1,G2;
output  [3:0]Y1,Y2;

assign Y1[0]  =  ~((~G1 & C1) & (~A & ~B));
assign Y1[1]  =  ~((~G1 & C1) & (~A &  B));
assign Y1[2]  =  ~((~G1 & C1) & ( A & ~B));
assign Y1[3]  =  ~((~G1 & C1) & ( A &  B));

assign Y2[0]  =  ~((~G2 & ~C2) & (~A & ~B));
assign Y2[1]  =  ~((~G2 & ~C2) & (~A &  B));
assign Y2[2]  =  ~((~G2 & ~C2) & ( A & ~B));
assign Y2[3]  =  ~((~G2 & ~C2) & ( A &  B));
   
endmodule

`timescale 100 ns/1 ns

module testbench;

/*

module ex4_74LS155 (A, B,C1,C2,G1,G2 ,Y1 , Y2);

input A,B,C1,C2,G1,G2;

output  [3:0]Y1,Y2;

*/

reg A,B,C1,G1,C2,G2;

wire [3:0]Y1,Y2;

integer i;

ex4_74LS155 UUT (A, B,C1,G1,C2,G2 ,Y1 , Y2);

initial

begin

A=1'b0 ;B=1'b0 ;C1=1'b0 ;C2=1'b0 ;G1=1'b0 ;G2=1'b0 ;

for (i=0;i<=15;i=i+1) begin

{C1,G1,A,B}=i;

#20;

end

for (i=0;i<=15;i=i+1) begin

{C2,G2,A,B}=i;

#20;

end

#20;  

$stop;

end

endmodule