以Verilog 設計一個數位電路 (EX1-2)--- 74LS151

以Verilog 設計一個數位電路 (EX1-2)--- 74LS151

`timescale 1 ns/1 ns
`timescale 1 ns/1 ns
module ex2_74LS151 ( D ,A, B, C ,S, Y , W);
input A,B,C,S;
input   [7:0]D;
output  Y,W;

assign W=~Y;

assign Y  =  ( D[0] & ~S & (~A & ~B & ~C)) |
  ( D[1] & ~S & (~A & ~B &  C)) |
  ( D[2] & ~S & (~A &  B & ~C)) |
  ( D[3] & ~S & (~A &  B &  C)) |    
  ( D[4] & ~S & ( A & ~B & ~C)) |
  ( D[5] & ~S & ( A & ~B &  C)) |
  ( D[6] & ~S & ( A &  B & ~C)) |    
  ( D[7] & ~S & ( A &  B &  C)) ;
   
endmodule

`timescale 100 ns/1 ns

module testbench;

/*

module ex2_74LS151 ( D ,A, B, C ,S, Y , W);

input A,B,C,S;

input   [7:0]D;

output  Y,W;

*/

reg A,B,C,S;

reg [7:0]D=8'b01010101;

wire Y,W;

integer i;

ex2_74LS151 UUT ( D ,A, B, C ,S, Y , W);

initial

begin

for (i=0;i<=15;i=i+1) begin

{S,A,B,C}=i;

#20;

end

#20;  

$stop;

end

endmodule