以Verilog 設計一個數位電路 (1)

以Verilog 設計一個數位電路 (1)

自動產生的Verilog 程式
module block1(
a,
b,
c,
d,
en,
sel,
f
);


input a;
input b;
input c;
input d;
input en;
input sel;
output f;

wire SYNTHESIZED_WIRE_0;
wire SYNTHESIZED_WIRE_1;
wire SYNTHESIZED_WIRE_2;
wire SYNTHESIZED_WIRE_3;

assign SYNTHESIZED_WIRE_2 = b | a;
assign SYNTHESIZED_WIRE_3 = d | c;

assign SYNTHESIZED_WIRE_0 = SYNTHESIZED_WIRE_2 & en;
assign SYNTHESIZED_WIRE_1 = en & SYNTHESIZED_WIRE_3;

Block2 b2v_inst12(
.I0(SYNTHESIZED_WIRE_0),
.sel(sel),
.I1(SYNTHESIZED_WIRE_1),
.Y(f));

endmodule

程式與測試平台

`timescale 1 ns/1 ns

module EX_101 (a, b, c, d, en, sel, f);

input  a, b, c, d, en, sel;

output f;

wire   f;

wire   g, h, i, j;

assign g = a | b;

assign i = g & en;

assign h = c | d;

assign j = h & en;

assign f = (sel==1'b0) ? i : j;

// f=   (  (sel' (a+b)*en) +  sel (c+d)*en  )

endmodule

//=========Test Bench===============

`timescale 100 ns/1 ns

module testbench;

reg a, b, c, d, en, sel;

wire f;

EX_101 UUT(

.a(a),

.b(b),

.c(c),

.d(d),

.en(en),

.sel(sel),

.f(f) );

initial

begin

 a   = 1'b0; // Time = 0

 b   = 1'b1;

 c   = 1'b0;

 d   = 1'b1;

 en  = 1'b0; sel = 1'b0;

 #10; // Time = 10

 en  = 1'b1; sel = 1'b0;

 #10; // Time = 20

 en  = 1'b0; sel = 1'b1;

 #10; // Time = 30

 en  = 1'b1; sel = 1'b1;

 #10 

 a   = 1'b1; // Time = 40

 b   = 1'b0;

 c   = 1'b1;

 d   = 1'b0;

 en  = 1'b0; sel = 1'b0; 

 #10; // Time = 50

 en  = 1'b1; sel = 1'b0;

 #10; // Time = 60

 en  = 1'b0; sel = 1'b1;

 #10; // Time = 70

 en  = 1'b1; sel = 1'b1;

 #10; // Time = 80

 $stop;

 end

endmodule