以Verilog 設計一個數位電路 (EX206)--- always --8bits 4x1 MUX電路

以Verilog 設計一個數位電路 (EX206)--- always --8bits 4x1 MUX電路

`timescale 1 ns/1 ns

module EX_206 (a, b, c, d, sel, e);
input [7:0] a, b, c, d;
input [1:0] sel;
output [7:0] e;
reg [7:0] e;

// non-behavioral writing style in EX_109 is also listed for
// comparison. e should be declared as wire in non-behavioral
// writing style.
//
// wire [7:0] e;
//
// assign e = (sel==2'b00) ? a :
//            (sel==2'b01) ? b :
//            (sel==2'b10) ? c : d;

always@( sel or a or b or c or d )
begin
case (sel)
  2'b00  : e = a;
  2'b01  : e = b;
  2'b10  : e = c;
  default : e = d;
endcase
end


endmodule

//===========================

`timescale 100 ns/1 ns

module testbench;

reg [7:0] a, b, c, d;

reg [1:0] sel;

wire [7:0] e;

EX_206 UUT(

.a(a),

.b(b),

.c(c),

.d(d),

.sel(sel),

.e(e) );

initial

begin

 a   = 8'h0a; // Time = 0

 b   = 8'h0b;

 c   = 8'h0c;

 d   = 8'h0d;

 sel = 2'b00;

 #20; // Time = 20

 sel = 2'b01;

 #20; // Time = 40

 sel = 2'b10;

 #20; // Time = 60

 sel = 2'b11;

 #20; // Time = 80

 $stop; 

end

endmodule