Shift Register using for loop in verilog

 Shift Register using  for loop in verilog
//======================================
module shift_reg_for_loop(
input CLK,
input RST,
input DATA_IN,
output BIT_OUT,
output [7:0] BYTE_OUT
);

//shift register signals
reg [7:0] bitShiftReg;
reg [7:0] byteShiftReg[3:0];  //4 x 8bit = 4 bytes
integer i;
//shift register
always @(posedge CLK or negedge RST) begin
if (~RST) begin
bitShiftReg=8'b0000_0000;
byteShiftReg[0]=8'b0000_0000;
byteShiftReg[1]=8'b0000_0000;
byteShiftReg[2]=8'b0000_0000;
byteShiftReg[3]=8'b0000_0000;
end
else
begin
//bit shift register
bitShiftReg <= {bitShiftReg[6:0],DATA_IN};
//byte shift register
byteShiftReg[0] <= bitShiftReg;
for(i=1;i<4;i=i+1)
byteShiftReg[i] <= byteShiftReg[i-1];

end
end
//module output wires
assign BIT_OUT = bitShiftReg[7];
assign BYTE_OUT = byteShiftReg[3];
endmodule

//======================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps   
module Test_bench;
/*
module shift_reg_for_loop(
input CLK,
input RST,
input DATA_IN,
output BIT_OUT,
output [7:0] BYTE_OUT);
*/
// Inputs
reg CLK=1'b0, RST=1'b1;
reg DATA_IN=1'b0;
// Outputs
wire BIT_OUT ;
wire [7:0] BYTE_OUT ;
integer i;

// Instantiate the Unit Under Test (UUT)

shift_reg_for_loop UUT (CLK, RST, DATA_IN, BIT_OUT , BYTE_OUT);

initial begin
  $monitor (CLK, RST, DATA_IN, BIT_OUT , BYTE_OUT);
  // Initialize Inputs
  #4  RST=0;
  #9  RST=1;
  end
always #5 CLK= ~CLK;

initial begin
 for(i =0; i<=20; i=i+1)
begin
#20 DATA_IN = ~DATA_IN;
end
#20 DATA_IN =1;
#20 DATA_IN = 1;
#20 DATA_IN =0;
#20 DATA_IN =1;
#20 DATA_IN = 1;
#20 DATA_IN =0;
#20 DATA_IN =1;
#20 DATA_IN = 1;
#20 DATA_IN =0;
 end 

initial
begin
    #420 // Final time:  300 ns
    $stop;
end
endmodule