Dataflow level Full Subtractor in Verilog

Dataflow level Full Subtractor in Verilog

//=============================================

// Dataflow level Full Subtractor in Verilog

//=============================================

`timescale 10ns/10ps 

module Full_subtractor(A,B,Bin,D,Bout);

input A,B,Bin;

output D,Bout;

assign D= A^B^Bin;

assign Bout=(~A&B) | (~A&Bin) | (B&Bin);

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Full_subtractor(A,B,Bin,D,Bout);

input A,B,Bin;

output D,Bout;

*/

reg A,B,Bin= 1'b0;   //  暫存器資料初值為‘0’

wire D,Bout;

integer i;

Full_subtractor UUT(A,B,Bin,D,Bout);

initial begin

    for (i=0; i<9; i=i+1) begin

         {A,B,Bin} = i;

         #20;

    end

    #20

     $stop;

end

endmodule