1 bit Full adder 全加器 (Gate level)

1 bit Full adder 全加器 (Gate level)

//=========================================
//定義一位元全加器
//(A ⊕ B) ⊕ Carry_in.  == Sum
// (A.B) or ( Carry_in A) or (A.C) === Carry_out
//=========================================
module Full_Adder(a,b,cin,sum,cout);
//宣告輸出入埠
input a,b,cin;

output sum,cout;

//宣告內部接線
wire net1,net2,net3;

xor u0(sum, a, b, cin);
and u1(net1, a, b);
and u2(net2, b, cin);
and u3(net3, cin, a);
or u4 (cout, net1, net2, net3);
endmodule

/* 

Full Adder Module for bit Addition 

*/

`timescale 100ns / 100ps 

 

module TB; 

/*

module Full_Adder (a,b,cin,sum,cout);

input a,b,cin;

output sum,cout;

*/

 

reg a;

reg b;

reg cin;

wire sum,cout;

Full_Adder UUT (a,b,cin,sum,cout);

 

initial

begin

a=1'b0; b=1'b0; cin=1'b0;

#5

a=1'b0; b=1'b0; cin=1'b1;

#5

a=1'b0; b=1'b1; cin=1'b0;

#5

a=1'b0; b=1'b1; cin=1'b1;

#5

a=1'b1; b=1'b0; cin=1'b0;

#5

a=1'b1; b=1'b0; cin=1'b1;

#5

a=1'b1; b=1'b1; cin=1'b0;

#5

a=1'b1; b=1'b1; cin=1'b1;

   

#5

$stop;

        

end

 

endmodule