4x1 MUX in Verilog

4x1 MUX in Verilog

//-------------------------------------------------------

//4-bit multiplexer with if...else if...else if...else...

//-------------------------------------------------------

module MUX_4x1(s, i ,y);

input [1:0] s;   //Select line

input [3:0] i;    //Input data

output reg y;

always @ (s or i)

  begin

    if (s==2'b00)

      y = i[0];

    else if (s==2'b01)

      y = i[1];

    else if (s==2'b10)

      y = i[2];

    else

      y = i[3];

  end

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module mul4_1_if(s, i ,y);

input [1:0] s;   //Select line

input [3:0] i;    //Input data

output reg y;

*/

// Inputs

    reg [1:0] s;

    reg [3:0] i;

// Outputs

    wire y;

// Instantiate the UUT

 MUX_4x1 UUT( 

        .y(y), 

        .s(s), 

        .i(i)  );

// Initialize Inputs

initial

 $monitor ($time,"y=%b, s=%b, i=%b", y, s, i);

initial //Initialize input signals

 begin

    s = 2'b00;

    i = 4'b0101;

 end

initial 

 begin

   #20  s = 2'b01;   //Set selection at different times

   #20  s = 2'b10;

   #20  s = 2'b11;

 end

initial #100 $finish;  //Complete simulation after 120 time units

  

endmodule