2x4 decoder 解碼器 in Verilog with gate level

2x4 decoder  解碼器 in Verilog with gate level

//------------------------------------
// 2-4 Decoder (Gate Level)
// Filename: decoder_2x4.v
//------------------------------------
module decoder_2x4(y, a, b);

// Port Declarations
output [3:0] y;  //outputs are y3, y2, y1, and y0
input a, b;

//Internal signal declarations
wire an, bn;

// Gate instantiations

// Create signals an and bn
not (an, a);
not (bn, b);

// And gates are instantiated
and (y[0], an, bn);
and (y[1], a, bn);
and (y[2], an, b);
and (y[3], a, b);

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module decoder_2x4(y, a, b);

// Port Declarations

output [3:0] y;  //outputs are y3, y2, y1, and y0

input a, b; 

*/

//inputs

reg a=1'b0;

reg b=1'b0;

//outputs

wire [3:0] y;

//instantiate the design module and connect to the testbench variables

decoder_2x4 UUT (y, a, b);

initial 

 begin

#50

a=1'b0; b=1'b1;

#50

a=1'b1; b=1'b0;

#50

a=1'b1; b=1'b1;

#50

$stop;

 end

 endmodule