//-----------------------------
// 2 bits comparator gate level
//-----------------------------
module comparator_2bit(a,b,L,G,E);
// Port Declarations
input [1:0]a,b ;
output L,G,E;
//Internal signal declarations
wire L1,E1,G1,L2,E2,G2;
wire E2L1,E2G1;
// Gate instantiations
compare U1(a[0], b[0], L1, E1,G1);
compare U2(a[1], b[1], L2, E2,G2);
and U3(E,E1,E2);
and U4(E2L1,E2,L1);
and U5(E2G1,E2,G1);
or U6(L,L2,E2L1);
or U7(G,G2,E2G1);
endmodule
module compare(a, b, L, E,G);
input a, b;
output L, E, G;
wire s1, s2;
not X1(s1, a);
not X2 (s2, b);
and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);
endmodule
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