RS Flip Flop with Enable in Verilog

RS Flip Flop with Enable in Verilog

//===========================================
// RS Flip Flop with Enable control
//===========================================
module RS_FF( en, S, R, Q, Qbar);
  input en, S, R;
  output Q, Qbar;
  wire Senbar,Renbar;
  
  assign Senbar = ~(en & S);
  assign Renbar = ~(en & R);
  
  RS_latch L1(Senbar, Renbar, Q, Qbar);
endmodule


module RS_latch(Sbar, Rbar, Q, Qbar);
  input Sbar, Rbar;
  output Q, Qbar;
  
  assign Q   = ~(Sbar & Qbar);
  assign Qbar= ~(Rbar & Q);

endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module RS_FF(input en, S, R, output Q, Qbar);
  input en, S, R;
  output Q, Qbar;
*/
reg S, en, R;
wire Q, Qbar;

RS_FF  UUT(en, S, R, Q, Qbar);


always #50 begin
  en = 1;
  #50;
  S = 1; R = 0;
  #50;
  S = 0; R = 0;
  #50;
  S = 0; R = 1;
  #50
  en = 0;
  #50;
  S = 1; R = 0;
  #50;
  S = 0; R = 0;
  #50;
  S = 0; R = 1;
end

initial #1000 $finish;


endmodule