1-bit half adder (Dataflow level)

1-bit half adder (Dataflow level)

//===============================
//1-bit half adder (Dataflow level)
//filename : half_add.v
//===============================
module half_add(a,b,s,cout);

input  a, b;
output s, cout;     // sum and carry out


assign s = a^ b;
assign cout = a & b;

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module half_add(a,b,s,cout);

input  a, b;

output s, cout;     // sum and carry out

*/

reg a,b;

wire s, cout;

integer i;

 

half_add UUT(a,b,s,cout);

 

initial begin  

   for ( i=0;i<=3;i=i+1) 

        begin

           {a,b}  = i;

            #10;

        end

end

endmodule