4-bit latch in Verilog

4-bit latch  in Verilog

//------------------------------------
//4-bit latch using if... statement
//------------------------------------
module Latch_4bit(load, din , y);

input load;     //latch signal
input [3:0] din;

output reg [3:0] y;

always @ (din or load)
 begin
  if (load)
    y = din;
 end
endmodule


// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps 
module TB;
/*
module Latch_4bit(load, din , y);
input load;     //latch signal
input [3:0] din;
output reg [3:0] y;
*/
// Inputs
    reg load;
    reg [3:0]din=4'b0000;

// Outputs
    wire [3:0] y;

// Instantiate the UUT
Latch_4bit UUT (load, din , y);
integer i;
initial begin
    for (i=0; i<32; i=i+1) begin
          {load,din} = i;
         #35;
    end
    #25
     $stop;
end


endmodule