4-bit 2 to 1 multiplexer using conditional operator dataflow level

4-bit 2 to 1 multiplexer using conditional operator dataflow level

//---------------------------------------------------
//4-bit 2 to 1 multiplexer using conditional operator
//filename :mux_2x1_4bit.v
//---------------------------------------------------
module mux_2x1_4bit(a,b,sel,y);

input [3:0] a, b;       // 4-bit input data
input sel;                // selection line
output [3:0] y;

assign y = (sel) ? a : b;

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module mux_2x1_4bit(a,b,sel,y);

input [3:0] a, b;       // 4-bit input data

input sel;                // selection line

output [3:0] y;

*/

reg [3:0] a, b;

reg sel;

wire [3:0] y;

integer i;

 

mux_2x1_4bit UUT(a,b,sel,y);

 

initial begin

   b=4'b0; sel=1'b1;

   for ( i=0;i<=15;i=i+1) 

        begin

            a=i;

            #10;

        end

   a=4'b0; sel=1'b0;

   for ( i=0;i<=15;i=i+1) 

        begin

            b=i;

            #10;

        end

   #10

$stop;

end

endmodule