1 bit comparator 比較器 in Verilog with gate level

1 bit comparator 比較器 in Verilog  with gate level

module compare(a, b, L, E,G);
input a, b;
output L, E, G;
wire s1, s2;

not X1(s1, a);
not X2 (s2, b);

and X3 (L,s1, b);
and X4 (G,s2, a);
xnor X5 (E, a, b);


endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module b_comp1 (a, b, L, E,G);

input a, b; 

output L, E, G;

*/

reg a=1'b0;

reg b=1'b0;

wire L,E,G;

compare UUT(a, b, L, E,G);

initial

begin

#50 

a=1'b0;b=1'b1;

#50 

a=1'b1;b=1'b0;

#50 

a=1'b1;b=1'b1;

#50 

$stop;

end

endmodule