Modulo-10 counter in Verilog

Modulo-10 counter in Verilog

//====================
module Mod_10(out,rst,clk);
output [3:0]out;
input clk,rst;
reg [3:0]out;

always @(posedge clk)
begin
if(rst|out==4'b1001)
out<=4'b0000;
else
out<=out+1;
end

endmodule

//====================

// 時間單位 1ns, 時間精確度1 ps

`timescale 100ns/10ps

module TB_Mod_10;

/*

module Mod_10(out,rst,clk);

output [3:0]out;

input clk,rst;

reg [3:0]out;

*/

  //input

  reg clk,rst;

    //output 

  wire [3:0]out;

 

  Mod_10 UUT (out,rst,clk);

  initial

     clk= 1'b0; 

  always

     #5  clk=~clk; 

  initial

     begin

       #2  rst=1'b1;

       #10 rst=1'b0;

       #500 $stop;

     end

 

   initial

       $monitor("clk=%b,rst=%b,out=%b",clk,rst,out);

endmodule

//====================