JK Flip Flop in Verilog

JK Flip Flop in Verilog

module JK_FF (j,k,clk,q);
   input j,k,clk;
   output reg q;

   always @ (posedge clk)
      case ({j,k})
         2'b00 :  q <= q;
         2'b01 :  q <= 0;
         2'b10 :  q <= 1;
         2'b11 :  q <= ~q;
      endcase
   
endmodule


 // 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
   reg j,k,clk=1'b0;
   wire q;
 
   JK_FF    UUT ( .j(j),
                  .k(k),
                  .clk(clk),
                  .q(q));
   always #5 clk = ~clk;

   initial begin
      j <= 1;
      k <= 0;
   
      #7  j <= 0;
          k <= 0;
      #27 j <= 0;
          k <= 1;
      #27 j <= 1;
          k <= 1;
      #20 $stop;
   end

   initial
      $monitor ("j=%0d k=%0d q=%0d", j, k, q);
endmodule

Info: ModelSim-Altera Info: # run -all
Info: ModelSim-Altera Info: # j=1 k=0 q=x
Info: ModelSim-Altera Info: # j=1 k=0 q=0
Info: ModelSim-Altera Info: # j=1 k=0 q=1
Info: ModelSim-Altera Info: # j=0 k=0 q=1
Info: ModelSim-Altera Info: # j=0 k=1 q=1
Info: ModelSim-Altera Info: # j=0 k=1 q=0
Info: ModelSim-Altera Info: # j=1 k=1 q=0
Info: ModelSim-Altera Info: # j=1 k=1 q=1
Info: ModelSim-Altera Info: # j=1 k=1 q=0