Dataflow 3 bits Majority in Verilog

Dataflow 3 bits Majority in Verilog

//========================
//Dataflow 3 bits Majority in Verilog
//========================
`timescale 10ns/10ps 
module major_3bit(I,Maj);
input [2:0]I;
output Maj;

assign Maj= (I[1] & I[0]) | ( I[2] & (I[1] | I[0]) ) ;

endmodule

//===============================

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module major_3bit(I,Maj);

input [2:0]I;

output Maj;

*/

reg [2:0]I= 3'b000;   //  暫存器資料初值為‘000’

wire Maj;

integer i;

major_3bit UUT(I,Maj);

initial begin

    for (i=0; i<9; i=i+1) begin

         {I} = i;

         #20;

    end

    #20

     $stop;

end

endmodule