Half Adder Structural Model in Verilog

Half Adder Structural Model in Verilog

源自於 https://electronicstopper.blogspot.com/2017/06/half-adder-structural-model-in-verilog.html

Code:

module xor1(input a, b, output s);
xor (s, a, b);
endmodule 

module and1(input a, b, output c);
and (c, a, b);
endmodule 

module halfadder8 (input a, b, output s, c);
xor1 u1(a, b, s);
and1 u2(a, b, c);
endmodule

Testbench Code:

module half_adder_verilog_tb();

reg a, b;
wire s, c;

halfadder8 dut (.a(a), .b(b), .s(s), .c(c));

initial
begin

a = 1'b0;
b = 1'b0;
#50;

a = 1'b0;
b = 1'b1;
#50;

a = 1'b1;
b = 1'b0;
#50;

a = 1'b1;
b = 1'b1;

end

endmodule

Output: