D-Flip flop 栓鎖電路 Gate Level in Verilog

D-Flip flop  栓鎖電路 Gate Level in Verilog

module D_latch(D,CLK,Q,Q_BAR);

input D,CLK;
output Q,Q_BAR;
wire X,Y;

nand U1 (X,D,CLK) ;
nand U2 (Y,X,CLK) ;
nand U3 (Q,Q_BAR,X);
nand U4 (Q_BAR,Q,Y);

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

wire Q,Q_BAR;

reg D,CLK;

D_latch UUT(D,CLK,Q,Q_BAR);

// Testbench of above code

initial begin

  $monitor("CLK = %b D = %b Q = %b Q_BAR = %b",CLK, D, Q, Q_BAR);

  CLK = 0;

  D = 0;

  #3 D = 1;

  #3 D = 0;

  #3 $stop;

end

always #2 CLK = ~CLK;

endmodule