RS Latch in Verilog

RS Latch in Verilog 

//===============

//Gate level
//===============

module RS_Latch(Sbar, Rbar, Q, Qbar);
input Sbar, Rbar;
output Q, Qbar;

  nand LS(Q, Sbar, Qbar);
  nand LR(Qbar, Rbar, Q);
endmodule

//===============

//Data flow level
//===============
module RS_Latch(Sbar, Rbar, Q, Qbar);
input Sbar, Rbar;
output Q, Qbar;

  assign Q   = ~(Sbar & Qbar);
  assign Qbar= ~(Rbar & Q);
endmodule

// 時間單位 1ns, 時間精確度10 ps
`timescale 10ns/10ps
module TB;
reg Sbar, Rbar;
wire Q, Qbar;

RS_Latch UUT(Sbar, Rbar, Q, Qbar);

always #50 begin
  Sbar = 0; Rbar = 1;
  #50;
  Sbar = 1; Rbar = 1;
  #50;
  Sbar = 1; Rbar = 0;
  #50;
end

initial #500 $finish;

endmodule