2-4 Decoder with enable 具有致能的解碼器 (Gate Level)

2-4 Decoder with enable 具有致能的解碼器 (Gate Level)

//------------------------------------
// 2-4 Decoder with enable (Gate Level)
// Filename: decoder_2x4_en.v
//------------------------------------

module decoder_2x4_en(in,en,Dout);

input [1:0] in;
input en;
output [3:0] Dout;

wire in0_0,in0_1;

not u1(in0_0,in[0]);
not u2(in0_1,in[1]);

and u4 (Dout[0],en,in0_0,in0_1);
and u5 (Dout[1],en,in[0],in0_1);
and u6 (Dout[2],en,in0_0,in[1]);
and u7 (Dout[3],en,in[0],in[1]);

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module decoder_2x4_en(in,en,Dout);

input [1:0] in;

input en;

output [3:0] Dout

*/

reg [1:0]in=2'b00;

reg en=1'b0;

wire [3:0] Dout;

integer i;

decoder_2x4_en UUT(in,en,Dout);

initial begin  

   for ( i=0;i<=8;i=i+1) 

        begin

           {en,in}  = i;

            #1;

        end

end

endmodule