4-bit 2 to 1 multiplexer in Verilog

4-bit 2 to 1 multiplexer in Verilog

//--------------------------------

//4-bit 2 to 1 multiplexer

//--------------------------------

module Mux2x1_4bit( s, a, b, y);

input s;           //Select signal

input [3:0] a, b;  //Input data

output reg [3:0] y;

always @ (s or a or b)

 if (s)

   y = b;

 else

   y = a;

endmodule

// 時間單位 1ns, 時間精確度10 ps

`timescale 10ns/10ps 

module TB;

/*

module Mux2x1_4bit( s, a, b, y);

input s;           //Select signal

input [3:0] a, b;  //Input data

output reg [3:0] y;

*/

// Inputs

    reg s;

    reg [3:0] a;

    reg [3:0] b;

// Outputs

    wire [3:0] y;

// Instantiate the UUT

Mux2x1_4bit UUT (

        .y(y), 

        .s(s), 

        .a(a), 

        .b(b)

        );

// Initialize Inputs

integer i;

initial begin

    b = 4'b1010; s=1'b0;

    for (i=0; i<16; i=i+1) begin

          a = i;

         #35;

    end

    a = 4'b0101; s=1'b1;

    for (i=0; i<16; i=i+1) begin

          b = i;

         #35;

    end

        

    

    #25

     $stop;

end

endmodule