4-1 Multiplexer 多工器 (Gate Level)

 4-1 Multiplexer 多工器 (Gate Level)

//------------------------------------
// 4-1 Multiplexer (Gate Level)
// Filename: mux_4x1.v
//------------------------------------
module mux_4x1(y, s, i);

// Port Declarations
output y;  //output y
input [1:0] s; // Data in : a, b;  Select: s
input [3:0] i;

//Internal signal declarations
wire y0, y1;

// Instantiates Q1, Q2, and Q3 with in-order manner
mux_2x1 U1 (y0, s[0], i[0], i[1]);
mux_2x1 U2 (y1, s[0], i[2], i[3]);
mux_2x1 U3 (y, s[1], y0, y1);

endmodule

//------------------------------------
// Filename: mux_2x1.v
//------------------------------------
module mux_2x1(y, s, a, b);

// Port Declarations
output y;  //output y
input s, a, b; // Data in : a, b;  Select: s

//Internal signal declarations
wire s0, sa, sb;

// Gate instantiations
not (s0, s);

// And gates are instantiated
and (sa, a, s0);
and (sb, b, s);
or (y, sa, sb);

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps 

module TB;

/*

module mux_4x1(y, s, i);

output y;  //output y

input [1:0] s; // Data in : a, b;  Select: s

input [3:0] i;

*/

//inputs

reg [3:0]i=4'b0000;

reg [1:0]s=2'b00;

//outputs

wire y;

integer k=0,j=0;

//instantiate the design module and connect to the testbench variables

mux_4x1  UUT(y, s, i);

initial

begin

for (k=0;k<=3;k=k+1)

begin

for (j=0;j<=15;j=j+1)

begin

#50 

s=k;

i=j;

end

end

#50 

$stop;

end

endmodule