Verilog code for EXOR gate – All modeling styles

Verilog code for EXOR gate – All modeling styles

Gate Level modeling

module XOR_2_gate_level(output Y, input A, B);
    xor (Y, A, B); 
endmodule

Data flow modeling

Equation of the XOR gate

The boolean equation of an XOR gate is Y = (A ⊕ B).

module XOR_2_data_flow (output Y, input A, B);
assign Y = A ^ B;
endmodule

Behavioral Modeling

Truth Table for XOR gate

A	B	Y(A XOR B)
0	0	0
0	1	1
1	0	1
1	1	0

Equation from the truth table

Y = A’B + AB’ or say Y = A XOR B.

module XOR_2_behavioral (output reg Y, input A, B);
always @ (A or B) begin
    if (A == 1'b0 & B == 1'b0) begin
        Y = 1'b0; 
   end   
   if (A == 1'b1 & B == 1'b1) begin
       Y = 1'b0; 
   end    
   else 
       Y = 1'b1; 
 end
endmodule

RTL schematic of XOR gate

Testbench of the XOR gate using Verilog

`include "XOR_2_behavioral.v"

`timescale 100ns/1ns
module XOR_2_behavioral_tb;
reg A, B;
wire Y;
XOR_2_behavioral Instance0 (Y, A, B);
initial begin   
 A = 0; B = 0;
 #10 A = 0; B = 1;
 #10 A = 1; B = 0; 
 #10 A = 1; B = 1; 

 #10 $stop;
end
initial begin  
  $monitor ("%t | A = %d| B = %d| Y = %d", $time, A, B, Y); 
  $dumpfile("dump.vcd"); 
  $dumpvars();
end
endmodule