2's Complement in Verilog (2'補數)

2's Complement in Verilog

1)gate level 
//=========================
//gate level HDL
//=========================
module two_complement(I,O);
input [3:0]I;
output [3:0]O;
wire w1,w2;

buf u1(O[0],I[0]);
xor u2(O[1],I[0],I[1]);
or  u3(w1,I[0],I[1]);
or  u4(w2,I[0],I[1],I[2]);
xor u5(O[2],I[2],w1);
xor u6(O[3],I[3],w2);


endmodule

Test bench

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps    

module Test_bench;

/*

module two_complement(I,O);

*/

// Inputs

reg [3:0]I=4'b0;

// Outputs

wire [3:0]O;

integer i;

// Instantiate the Unit Under Test (UUT)

two_complement UUT (I,O);

initial begin

  $monitor (I,O);

 for(i =0; i<=20; i=i+1)

begin

#20 I= I+1;

end  

end

endmodule

2) DataFlow Level

//=========================

//Dataflow level HDL

//=========================

// & bit-wise AND

// ^ bit-wise XOR

// | bit-wise OR

module two_complement(I,O);

input [3:0]I;

output [3:0]O;

assign O[0]=I[0];

assign O[1]= (I[0] ^ I[1]);

assign O[2]= (I[2] ^ (I[1] | I[0]));

assign O[3]= (I[3] ^ (I[2] | I[1] | I[0]));

endmodule

3) Behavior Level Case

//=========================

//Behavior level HDL : Case

//=========================

// & bit-wise AND

// ^ bit-wise XOR

// | bit-wise OR

module two_complement(I,O);

input [3:0]I;

output reg [3:0]O;

always @(*) begin

case (I) 

0: O=4'b0000;

1: O=4'b1111;

2: O=4'b1110;

3: O=4'b1101;

4: O=4'b1100;

5: O=4'b1011;

6: O=4'b1010;

7: O=4'b1001;

8: O=4'b1000;

9: O=4'b0111;

10: O=4'b0110;

11: O=4'b0101;

12: O=4'b0100;

13: O=4'b0011;

14: O=4'b0010;

15: O=4'b0001;

endcase

end

endmodule

4) Behavior Level  if else

//=========================

//Behavior level HDL : if else

//=========================

// & bit-wise AND

// ^ bit-wise XOR

// | bit-wise OR

module two_complement(I,O);

input [3:0]I;

output reg [3:0]O;

always @(*) begin

if(I==4'd0) 

O=4'b0000;

else if (I==4'd1)

O=4'b1111;

else if (I==4'd2)

O=4'b1110;

else if (I==4'd3)

O=4'b1101;

else if (I==4'd4)

O=4'b1100;

else if (I==4'd5)

O=4'b1011;

else if (I==4'd6)

O=4'b1010;

else if (I==4'd7)

O=4'b1001;

else if (I==4'd8)

O=4'b1000;

else if (I==4'd9)

O=4'b0111;

else if (I==4'd10)

O=4'b0110;

else if (I==4'd11)

O=4'b0101;

else if (I==4'd12)

O=4'b0100;

else if (I==4'd13)

O=4'b0011;

else if (I==4'd14)

O=4'b0010;

else

O=4'b0001;

end

endmodule