HBLbits_Verilog Basic_Lemmings2

HBLbits_Verilog Basic_Lemmings2 

See also: Lemmings1.

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

該題在上一題的基礎上添加了掉落的狀態fall，輸入信號中多了ground信號，當ground=1時表示在地面上，ground=0時表示在掉落中。輸出信號多了aaah信號，表示掉落狀態時的尖叫聲啊啊啊hhh。這裡需要注意的是掉落著陸後的方向問題，題目也明確指出方向與掉落前一致。另外需要注意的是在掉落過程中walk_left/right的狀態輸出均為0。波形圖如下

雖然掉落時不區分方向，輸出只有aaah，但是著陸後的方向與掉落前方向一致，所以這裡將掉落狀態分為兩個狀態更為方便，即向左走的時候發生掉落fall_l和向右走的時候發生掉落fall_r狀態。這樣當著陸後直接返回相應的left和right狀態即可。所以fall_l和fall_r狀態之間也不能發生轉換。狀態機描述如下

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    parameter left = 0,right = 1,fall_l = 2,fall_r = 3;
    
    reg[1:0] state, next_state;
    reg[2:0] out;
  
    //state
    always@(posedge clk or posedge areset) begin
        if(areset)
            state <= left;
        else
            state <= next_state;
    end
    
    //transition
    always@(*)begin
        case(state)
            left    : next_state= ground ? (bump_left?right:left) : fall_l;
            right : next_state= ground ? (bump_right?left:right) : fall_r;
            fall_l: next_state= ground ? left:fall_l;
            fall_r: next_state= ground ? right:fall_r;
        endcase
    end
    
    //out
    always@(posedge clk or posedge areset) begin
        if(areset)
             out <= 3'b100;
        else
            case(next_state)
                left      : out      <= 3'b100;
                fall_l: out <= 3'b001;
                right : out <= 3'b010;
                fall_r: out <= 3'b001;
            endcase
    end
    
    assign {walk_left, walk_right, aaah} = out;
endmodule