HBLbits_Verilog Basic_Exams/review2015 fsmseq

HBLbits_Verilog Basic_Exams/review2015 fsmseq

Sequence 1101 recognizer

This is the second component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Getting stuck in the final state is intended to model going to other states in a bigger FSM that is not yet implemented. We will be extending this FSM in the next few exercises.

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    parameter S0=0,S1=1,S2=2,S3=3,S4=4;
    reg [2:0] cs,ns;
    
    always @(*)
        begin
            case (cs)
                S0:ns=data?S1:S0;
                S1:ns=data?S2:S0;
                S2:ns=data?S2:S3;
                S3:ns=data?S4:S0;
                S4:ns=data?S4:S4;
            endcase
        end
    always @(posedge clk)
        begin
            if (reset)
                cs<=S0;
            else
                cs<=ns;
        end
    assign start_shifting= (cs==S4);
endmodule

module top_module (

    input clk,

    input reset,      // Synchronous reset

    input data,

    output start_shifting);

    parameter S0=0,S1=1,S2=2,S3=3,S4=4;

    reg [2:0]state,next;

    always@(posedge clk)

    if(reset)

            state <= S0;

    else

            state <= next;

    always@(*)

        case(state)

            S0:next=data?S1:S0;

            S1:next=data?S2:S0;

            S2:next=data?S2:S3;

            S3:next=data?S4:S0;

            S4:next=S4;

            default:next=S0;

        endcase

    always@(posedge clk)

        if(reset)

            start_shifting <= 0;

    else if(next==S4) //注意此处的状态是next;

            start_shifting <= 1;

endmodule