Basics
Zero
output zero
);// Module body starts after semicolon
assign zero=1'b0;
endmodule
Wire
module top_module( input in, output out );
wire w1;
assign w1=in;
assign out=w1;
endmodule
Wire4
a -> w
b -> x
b -> y
c -> z
module top_module(
input a,b,c,
output w,x,y,z );
wire w1,w2,w3,w4;
assign w1=a;
assign w2=b;
assign w3=b;
assign w4=c;
assign w=w1;
assign x=w2;
assign y=w3;
assign z=w4;
endmodule
Notgate
module top_module( input in, output out );
assign out=~(in);
endmodule
Andgate
module top_module(
input a,
input b,
output out );
assign out= a&b;
endmodule
Norgate
module top_module(
input a,
input b,
output out );
assign out=~(a|b);
endmodule
Xnorgate
module top_module(
input a,
input b,
output out );
assign out= ~(a^b);
endmodule
Wire
decl
module top_module (
input in, // Declare an input wire named "in"
output out // Declare an output wire named "out"
);
wire not_in; // Declare a wire named "not_in"
assign out = ~not_in; // Assign a value to out (create a NOT gate).
assign not_in = ~in; // Assign a value to not_in (create another NOT gate).
endmodule // End of module "top_module"
`default_nettype none
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1,w2,w3;
assign w1=a&b;
assign w2=c&d;
assign w3=w1|w2;
assign out=w3;
assign out_n=~w3;
endmodule
7458
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
wire w1,w2,w3,w4;
assign w1=p1a & p1b & p1c;
assign w2=p1d & p1e & p1f;
assign p1y=w1 | w2;
assign w3=p2a & p2b ;
assign w4=p2c & p2d ;
assign p2y=w3 | w4;
endmodule
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