HBLbits_Verilog Basic_Exams/review2015 fsm

HBLbits_Verilog Basic_Exams/review2015 fsm 

This is the fourth component in a series of five exercises that builds a complex counter out of several smaller circuits. See the final exercise for the overall design.

You may wish to do FSM: Enable shift register and FSM: Sequence recognizer first.

We want to create a timer that:

1. is started when a particular pattern (1101) is detected,
2. shifts in 4 more bits to determine the duration to delay,
3. waits for the counters to finish counting, and
4. notifies the user and waits for the user to acknowledge the timer.

In this problem, implement just the finite-state machine that controls the timer. The data path (counters and some comparators) are not included here.

The serial data is available on the data input pin. When the pattern 1101 is received, the state machine must then assert output shift_ena for exactly 4 clock cycles.

After that, the state machine asserts its counting output to indicate it is waiting for the counters, and waits until input done_counting is high.

At that point, the state machine must assert done to notify the user the timer has timed out, and waits until input ack is 1 before being reset to look for the next occurrence of the start sequence (1101).

The state machine should reset into a state where it begins searching for the input sequence 1101.

Here is an example of the expected inputs and outputs. The 'x' states may be slightly confusing to read. They indicate that the FSM should not care about that particular input signal in that cycle. For example, once a 1101 pattern is detected, the FSM no longer looks at the data input until it resumes searching after everything else is done.

創建一個計時器，當檢測到序列1101時啟動，接著等待4位，然後計數器完成計數，最後等待用戶確認計數器。這其實就是前面幾道題目的組合。

創建一個計時器：①當檢測到特定模式（1101）時啟動；②再移4位以確定延遲時間；③等待計數器完成計數，然後通知用戶並等待用戶確認計時器。

當接收到模式1101時，狀態機必須在4個時鐘週期內斷言輸出shift_ena。此後，狀態機聲明其計數輸出以指示其正在等待計數器，並等待直到輸入done_counting為高。

串列資料在資料登錄引腳上可用。當接收到模式1101時，電路必須隨後移入接下來的4位，即最高有效位在前。這4位確定計時器延遲的持續時間。將其稱為delay [3：0]。

此後，狀態機聲明其計數輸出以指示其正在計數。狀態機必須精確計數（delay [3：0] + 1）* 1000個時鐘週期。例如，delay = 0表示計數1000個週期，而delay = 5表示計數6000個週期。同時輸出當前剩餘時間。這應該等於1000個週期的延遲，然後等於1000個週期的delay-1，依此類推，直到1000個週期為0。當電路不計數時，count [3：0]輸出無關緊要。

此時，電路必須斷言完成，以通知用戶計時器已超時，並等待直到輸入ack為1才復位，以查找下一次出現的啟動序列（1101）。電路應重置為開始搜索輸入序列1101的狀態。

這是預期輸入和輸出的示例。“ x”狀態可能會使閱讀有些混亂，它們表明FSM在該週期中不應關心該特定輸入信號。例如，一旦讀取了1101和delay [3：0]，電路將不再查看資料登錄，直到在完成所有其他操作後恢復搜索為止。在此示例中，電路的計數為2000個時鐘週期，因為delay [3：0]值為4'b0001。最後幾個週期以delay [3：0] = 4'b1110開始另一個計數，該計數將計數15000個週期。

module top_module (

    input clk,

    input reset,      // Synchronous reset

    input data,

    output shift_ena,

    output counting,

    input done_counting,

    output done,

    input ack );

   parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, COUNT=8, WAIT=9;

    reg [3:0] current_state;

    reg [3:0] next_state;

    

    always@(posedge clk)begin

        if(reset)begin

            current_state <= S;

        end

        else begin

            current_state <= next_state;

        end

    end

    

    always@(*)begin

        case(current_state)

            S:begin

                next_state = data ? S1 : S;

            end

            S1:begin

                next_state = data ? S11 : S;

            end

            S11:begin

                next_state = data ? S11 : S110;

            end

            S110:begin

                next_state = data ? B0 : S;

            end

            B0:begin

                next_state = B1;

            end

            B1:begin

                next_state = B2;

            end

            B2:begin

                next_state = B3;

            end

            B3:begin

                next_state = COUNT;

            end

            COUNT:begin

                next_state = done_counting ? WAIT : COUNT;

            end

            WAIT:begin

                next_state = ack ? S : WAIT;

            end

            default:begin

                next_state = S;

            end

        endcase

    end

    

    assign shift_ena = (current_state == B0 || current_state == B1 || current_state == B2 || current_state == B3);

    assign counting = (current_state == COUNT);

    assign done = (current_state == WAIT);

endmodule