HBLbits_Verilog Basic_Exams/ece241 2013 q8

HBLbits_Verilog Basic_Exams/ece241 2013 q8

Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have an active-low asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences.

Fig. 7.1 State diagrams for Edge detector : Moore Design

Fig. 7.2 State diagrams for Edge detector : Mealy Design

mealy型狀態機序列檢測的問題，檢測“101”序列。注意，題目中要求重疊檢測，比如“10101”，z應該兩次拉高，其他應該就沒什麼難度了。

module top_module (
    input clk,
    input aresetn,    // Asynchronous active-low reset
    input x,
    output z );

 
    localparam  // 3 states are required for Mealy
    a = 2'b00,
    b = 2'b01,
    c = 2'b10;
    reg[1:0] state, next_state; 
    
    always @(posedge clk, negedge aresetn)
begin
        if(~aresetn) // go to state zero if rese
        begin
        state<= a;
        end
        else // otherwise update the states
        begin
        state <= next_state;
        end
end
    
    always@(*)begin
case(state)
            a:begin
                next_state=x?b:a;
            end
            b:begin
                next_state=x?b:c;
            end
            c:begin
                next_state=x?b:a;
            end
            default:begin
                next_state=a;
            end
        endcase
    end
    
    always@(*)begin
        case(state)
            a:begin
                z = 1'b0;
            end
            b:begin
                z = 1'b0;
            end
            c:begin
                z = x;
            end
        endcase
    end
  
endmodule