HBLbits_Verilog Basic_Exams/ece241 2014 q5a

HBLbits_Verilog Basic_Exams/ece241 2014 q5a 

You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires an asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted.
For example:

Example-1:

1. Lets take 001 and we know that its 2’s complement is (110+1 = 111).
2. So scan from right to left.
3. On state A ‘1’ came first to go to stage B and in output write 1.
4. On state B replace ‘0’ with ‘1’ and vice-versa.
5. So finally we got 111 as output.
6. Be aware that the output is also printed in right to left order.

Example-2:

1. Lets take 01 and we know that its 2’s complement is (10+1 = 11).
2. So scan from right to left.
3. On state A ‘1’ came first to go to stage B and in output write 1.
4. On state B replace ‘0’ with ‘1’ and vice-versa.
5. So finally we got 11 as output.
6. Be aware that the output is also printed in right to left order.

1's Complement

2's Complement

module top_module (
    input clk,
    input areset,
    input x,
    output z
); 
    localparam A = 0, B = 1, C = 2, D = 3;
    reg [1:0] state, next_state;
    always@(*) begin
        case(state)
            A: begin
                if(x) next_state = B;
                else next_state = A;
            end
            B: begin
                if(x) next_state = D;
                else next_state = C;
            end
            C: begin
                if(x) next_state = D;
                else next_state = C;
            end
            D: begin
                if(x) next_state = D;
                else next_state = C;
            end
            default: begin
                next_state = A;
            end
            
        endcase
    end
    always@(posedge clk or posedge areset) begin
        if(areset) state <= A;
        else state <= next_state;    
    end
    
    assign z = (state == B || state == C)? 1 : 0;
endmodule