HBLbits_Verilog Basic_Exams/2012 q2b

HBLbits_Verilog Basic_Exams/2012 q2b

 The state diagram for this question is shown again below.

Assume that a one-hot code is used with the state assignment y[5:0] = 000001(A), 000010(B), 000100(C), 001000(D), 010000(E), 100000(F)

Write a logic expression for the signal Y1, which is the input of state flip-flop y[1].

Write a logic expression for the signal Y3, which is the input of state flip-flop y[3].

(Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

module top_module (

    input [5:0] y,

    input w,

    output Y1,

    output Y3

);

    parameter A=6'b000001,B=6'b000010,C=6'b000100;

    parameter D=6'b001000,E=6'b010000,F=6'b100000;

    reg[5:0] current_state, next_state;

    always@(*)begin

        case(current_state)

            A: next_state = w?B:A;

            B: next_state = w?C:D;

            C: next_state = w?E:D;

            D: next_state = w?F:A;

            E: next_state = w?E:D;

            F: next_state = w?C:D;

            default: next_state = A;

        endcase

    end

  

    assign Y1 = (y[0] & w) ;

    assign Y3 = ~w & (y[1] | y[2] | y[4]| y[5]) ;   

endmodule