HBLbits_Verilog Multiplexers
Multiplexers
Mux2to1
Create a one-bit wide, 2-to-1 multiplexer. When
sel=0, choose a. When sel=1, choose b.
|
module top_module( input a, b, sel, output out );
assign out = (sel==1) ? b: a; endmodule |
Mux2to1v
Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.
|
module top_module( input [99:0] a, b, input sel, output [99:0] out ); assign out= (sel) ? b:a ; endmodule |
Mux9to1v
Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.
|
module top_module( input [15:0] a, b, c, d, e, f, g, h, i, input [3:0] sel, output [15:0] out );
assign out = (sel==3'b000)?a: (sel==4'b0001)?b: (sel==4'b0010)?c: (sel==4'b0011)?d: (sel==4'b0100)?e: (sel==4'b0101)?f: (sel==4'b0110)?g: (sel==4'b0111)?h: (sel==4'b1000)?i: 16'hffff;
endmodule |
Mux256to1
Create a 1-bit wide, 256-to-1 multiplexer. The
256 inputs are all packed into a single 256-bit input vector. sel=0 should
select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.
|
module top_module( input [255:0] in, input [7:0] sel, output out ); integer i;
assign out = in[sel]; endmodule |
Mux256to1v
Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
|
module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out ); assign out = {in[sel * 4 + 3], in[sel * 4 + 2], in[sel * 4 + 1], in[sel * 4]}; endmodule |
|
module top_module( input [1023:0] in, input [7:0] sel, output [3:0] out );
assign out = in[sel*4 +: 4]; //in[sel * 4 +: 4]代表从0开始向上数4位，即in[3:0] endmodule |
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