Verilog Binary to Gray code

Verilog Binary to Gray code

module bin2gray
        (input [3:0] bin, //binary input
         output [3:0] G //gray code output
        );

//xor gates.
assign G[3] = bin[3];
assign G[2] = bin[3] ^ bin[2];
assign G[1] = bin[2] ^ bin[1];
assign G[0] = bin[1] ^ bin[0];

endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg [3:0] t_bin = 4'b0000;   //  暫存器資料初值為‘0’

wire [3:0]t_G;

integer i;

bin2gray  DUT(.bin(t_bin), .G(t_G));
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(t_bin,t_G);
    for (i=0; i<16; i=i+1) begin
        {t_bin} = i;
        #20;
    end
end

initial
begin
  #340;   // 模擬終止時間  200 ns
    $stop;
end

endmodule