4 bit adder/subtractor verilog

4 bit adder/subtractor verilog

module Add_Sub_4bit (
output [3: 0] S,
output C,
input [3: 0] A, B,
input M  //ADD =0  / SUB=1 
);
wire [3: 0] B_xor_M;
wire C1, C2, C3, C4;

assign C = C4; // output carry
xor (B_xor_M[0], B[0], M);
xor (B_xor_M[1], B[1], M);
xor (B_xor_M[2], B[2], M);
xor (B_xor_M[3], B[3], M);

// Instantiate full adders
full_adder FA0 (S[0], C1, A[0], B_xor_M[0], M);
full_adder FA1 (S[1], C2, A[1], B_xor_M[1], C1);
full_adder FA2 (S[2], C3, A[2], B_xor_M[2], C2);
full_adder FA3 (S[3], C4, A[3], B_xor_M[3], C3);

endmodule

module full_adder (output S, C, input x, y, z); // See HDL Example 4.2
wire S1, C1, C2;
// instantiate half adders
half_adder HA1 (S1, C1, x, y);
half_adder HA2 (S, C2, S1, z);
or G1 (C, C2, C1);
endmodule

module half_adder (output S, C, input x, y); // See HDL Example 4.2
xor (S, x, y);
and (C, x, y);

endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module test;
   
reg [3:0] t_A=4'b0000;
reg [3:0] t_B=4'b0000;
reg t_M=1'b0;   
wire [3:0] t_S;
wire t_C;

integer i;
   
Add_Sub_4bit  DUT (.S(t_S),.C(t_C),.A(t_A),.B(t_B),.M(t_M));
   
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(t_A,t_B,t_M,t_S,t_C);
    for (i=0; i<16; i=i+1) begin
        {t_A} = 4'b0100;
        {t_B} = i;
        t_M=1'b0;
        #20;
    end
 
      for (i=0; i<16; i=i+1) begin
        {t_A} = i;
        {t_B} = 4'b0100;
        t_M=1'b1;
        #20;
    end
   
 
end

initial
begin
  #720;   // 模擬終止時間  400 ns
    $stop;
end
   

endmodule