Verilog 4-Bit Magnitude Comparator

Verilog  4-Bit Magnitude Comparator 

     A < B

1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

    A > B

1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0

    A = B     

       (A3 Ex-Nor B3) (A2 Ex-Nor 82) (Al Ex-Nor BI) (AO Ex-Nor BO)

 //4-bit comparator is designed and implemented in Verilog HDL

 module comparator_4bit(input [3:0] A,B, output A_less_B, A_equal_B, A_greater_B); 
 wire tmp10,tmp11,tmp12,tmp13;
 wire tmp20,tmp21,tmp22,tmp23;
 wire tmp30,tmp31,tmp32,tmp33;
 wire tmp40,tmp41,tmp42;

 // A = B output 
 xnor u1(tmp13,A[3],B[3]); 
 xnor u2(tmp12,A[2],B[2]);
 xnor u3(tmp11,A[1],B[1]); 
 xnor u4(tmp10,A[0],B[0]); 
 and  u5(A_equal_B,tmp10,tmp11,tmp12,tmp13);

 assign tmp40 = (~A[3]& ~B[3]) | (A[3] & B[3]);
 assign tmp41 = (~A[2]& ~B[2]) | (A[2] & B[2]);
 assign tmp42 = (~A[1]& ~B[1]) | (A[1] & B[1]);
 
 // A less than B output 
 assign tmp20 = (~A[3]& B[3]); 
 assign tmp21 = ( tmp40 & (~A[2] & B[2]));
 assign tmp22 = ( tmp40 & tmp41 & (~A[1] & B[1])); 
 assign tmp23 = ( tmp40 & tmp41 & tmp42 & (~A[0] & B[0]));
 assign A_less_B = tmp20 | tmp21 | tmp22 | tmp23 ;
 
 // A greater than B output 
 assign tmp30 = (A[3]& ~B[3]); 
 assign tmp31 = ( tmp40 & (A[2]& ~B[2]));
 assign tmp32 = ( tmp40 & tmp41 & (A[1] & ~B[1])); 
 assign tmp33 = ( tmp40 & tmp41 & tmp42 & (A[0] & ~B[0]));
 assign A_greater_B = tmp30 | tmp31 | tmp32 | tmp33 ;

 endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
 // Verilog testbench code for 4-bit comparator   
 module tb_comparator;  
 reg [3:0] A, B; 
 wire A_less_B, A_equal_B, A_greater_B; 
 integer i; 
 // device under test 
comparator_4bit DUT(A,B,A_less_B, A_equal_B, A_greater_B); 
 initial begin 
      for (i=4;i<8;i=i+1) 
      begin 
           A = i; 
           B = i + 1; 
           #20; 
      end 
      for (i=0;i<4;i=i+1) 
      begin 
           A = i; 
           B = i; 
           #20; 
      end 
      for (i=10;i<16;i=i+1) 
      begin 
           A = i+1; 
           B = i; 
           #20; 
      end 
 end 
 endmodule