範例 EX5_13 Verilog code for BCD to 7-segment display converter

Verilog code for BCD to 7-segment display converter

 

//EX5-13_p162
module EX5_13_p162(A,seg);

input  [3:0]A ; // A 4位元輸入
output [6:0]seg;     // Output    1位元輸出
reg [6:0]seg;

always@(A)
begin
 case(A)
  4'b0000: seg =7'b111_0111;    //0
  4'b0001: seg =7'b010_0100; //1
  4'b0010: seg =7'b101_1101; //2
  4'b0011: seg =7'b101_1011; //3
  4'b0100: seg =7'b011_1010; //4
  4'b0101: seg =7'b110_1011; //5
  4'b0110: seg =7'b110_1111; //6
  4'b0111: seg =7'b101_0010; //7

  4'b1000: seg =7'b111_1111; //8
  4'b1001: seg =7'b111_1010; //9
//switch off 7 segment character when the bcd digit is not a decimal number.
  default : seg = 7'b000_0000; 

 endcase
end

endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
reg [3:0]t_A = 4'b0000;   //  暫存器資料初值為‘0000’
wire [6:0]t_seg;

integer i;

EX5_13_p162  DUT(.A(t_A),.seg(t_seg) );
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(t_A,,t_seg);
    for (i=0; i<16; i=i+1) begin
        {t_A} = i;
        #20;
    end
end

initial
begin
  #340;   // 模擬終止時間  200 ns
    $stop;
end

endmodule