Four-Bit Adder in Verilog

module fullAdder(
   input a,
   input b,
   input carryIn,
   output sum,
   output carryOut
);
    assign {carryOut,sum}=carryIn+a+b;
endmodule


module four_bit_Adder(
    input [3:0] a,
    input [3:0] b,
    output [3:0] sum,
    output cout
    );
   
 wire cy_w1, cy_w2, cy_w3;
 // instantiating 4 1-bit full adders in Verilog
 //module fullAdder(a, b , carryIn , fa_sum , carryOut);
 fullAdder u1(a[0], b[0], 1'b0,  sum[0], cy_w1);
 fullAdder u2(a[1], b[1], cy_w1, sum[1], cy_w2);
 fullAdder u3(a[2], b[2], cy_w2, sum[2], cy_w3);
 fullAdder u4(a[3], b[3], cy_w3, sum[3], cout);

endmodule


// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps     
module test;
   
reg [3:0] t_a;
reg [3:0] t_b;
   
wire [3:0] t_sum;
wire t_cout;

integer i;
   
four_bit_Adder DUT (.a(t_a),.b(t_b),.sum(t_sum),.cout(t_cout));
   
// initial程序結構區塊, 產生A、B輸入信號波形
initial begin
    $monitor(t_a,t_b,t_sum,t_cout);
    for (i=0; i<16; i=i+1) begin
        {t_a} = i;
        {t_b} = i;
       
        #20;
    end
end

initial
begin
  #360;   // 模擬終止時間  400 ns
    $stop;
end
   
endmodule