D latch verilog code

D latch verilog code

module D_Latch(
   input      D,
   input      En,
   output reg Q=1'b0,
   output wire Qbar=1'b1 
);

always@(D or En)
   if (En)
     Q    <= D ;
     assign Qbar = ~Q ;

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

    reg  D,En;

    wire Q,Qbar;

//module D_Latch(input D,input En,output reg Q=1'b0,output Qbar=1'b1);

D_Latch DUT(

.D(D),

.En(En),

.Q(Q),

.Qbar(Qbar) );

    

initial begin

    

    $monitor(D,En,Q,Qbar);

    // Initialize Inputs

    D = 0;

    En = 1; 

    // Add stimulus here

    #100 D = 0; 

    #100 D = 1;  

    #100 D = 1;  

    #100 D = 1;  

    #100 D = 0;  

    #100 D = 1;  

    #100 D = 0;  

    

    En = 0;

    #100 D = 0; 

    #100 D = 1;  

    #100 D = 1;  

    #100 D = 1;  

    #100 D = 0;  

    #100 D = 1;  

    #100 D = 0; 

    

    

    #100 ;  $stop;

end

endmodule

SR Latch (Enable) Verilog

SR Latch (Enable)   Verilog

module SR_Latch(
           input  S, R, En,
           output Q, Qbar);

   wire   S2   = ~(En & S);
   wire   R2   = ~(En & R);
   assign Q    = ~(S2 & Qbar);
   assign Qbar = ~(R2 & Q);

endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
    reg  S,R,En;
    wire Q,Qbar;

//SR_Latch( input wire S, R, En, output wire Q, Qbar);

SR_Latch DUT(
.S(S),
.R(R),
.En(En),
.Q(Q),
.Qbar(Qbar) );
   
initial begin
   
    $monitor(S,R,En,Q,Qbar);
    // Initialize Inputs
    S = 0;
    R = 1;
    En = 1; 
    // Add stimulus here
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0;
   
    En = 0;
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0; 
   
   
    #100 ;  $stop;
end
endmodule

SR Latch (gated) Verilog

SR Latch (gated) Verilog

module SR_Latch_gated(S,R,G,Q,Qn);
   output Q;
   output Qn;
   input  G; 
   input  S;
   input  R;

   wire   S1;
   wire   R1;
 
   and(S1, G, S);
   and(R1, G, R); 
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
 

endmodule



// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps
module Test_bench;
    reg  S,R,G;
    wire Q,Qn;

//SR_Latch_gated(S,R,G,Q,Qn);

SR_Latch_gated  DUT(
.S(S),
.R(R),
.G(G),
.Q(Q),
.Qn(Qn) );
   
initial begin
   
    $monitor(S,R,G,Q,Qn);
    // Initialize Inputs
    S = 0;
    R = 1;
    G = 1;
    // Add stimulus here
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0;
   
    G = 0;
    #100 S = 0; R = 1;
    #100 S = 1; R = 0;
    #100 S = 1; R = 1;
    #100 R = 1; R = 0;
    #100 S = 0; R = 0;
    #100 S = 1; R = 1;
    #100 S = 0; R = 0; 
   
   
    #100 ;  $stop;
end

endmodule

NOR Gate Latch Verilog

NOR Gate Latch  Verilog

// file: sr_latch.v

// Using Verilog to describe our SR Latch

module SR_Latch(

    input wire S, R,

    output wire Q, Qn);

    assign Q   =  ~(R | Qn);

    assign Qn  =  ~(S | Q);

    

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

    reg  S,R;

    wire Q,Qn;

SR_Latch  DUT(

.S(S),

.R(R),

.Q(Q),

.Qn(Qn) );

    

initial begin

    

    $monitor(S,R,Q,Qn);

    // Initialize Inputs

    S = 0;

    R = 0;

     

    // Add stimulus here

    #100 S = 0; R = 1;

    #100 S = 1; R = 0;

    #100 S = 1; R = 1;

    #100 R = 1; R = 0;

    #100 S = 0; R = 0;

    #100 S = 1; R = 1;

    #100 S = 0; R = 0;

    #100 ;  $stop;

end

endmodule

Verilog SR latch

Verilog SR latch

module RS_Latch(

    input S,

    input R,

    output Q,

    output Qn

    );

wire Q_int, Qn_int;

assign Q_int = ~(S & Qn_int);

assign Qn_int = ~(R & Q_int);

assign Q = Q_int;

assign Qn = Qn_int;

endmodule

// 時間單位 100ns, 時間精確度100 ps

`timescale 100ns/100ps

module Test_bench;

    reg  S,R;

    wire Q,Qn;

RS_Latch  DUT(

.S(S),

.R(R),

.Q(Q),

.Qn(Qn) );

    

initial begin

    

    $monitor(S,R,Q,Qn);

    // Initialize Inputs

    S = 0;

    R = 1;

     

    // Add stimulus here

    #100 S = 0;

    #100 S = 1;

    #100 R = 0;

    #100 R = 1;

    #100 S = 0;

         R = 0;

    #100 S = 1;

         R = 1;

    #100 S = 0;

         R = 0;

    #100 ;  $stop;

end

endmodule

SR-Latch

SR-Latch

https://learn.digilentinc.com/Documents/255

SR-Latch NAND Cell

Related Material:

Latch

Figure 1 below shows an implementation for SR-Latch with NAND implementation. According to the truth table on the right, S and R are active low. When only S is asserted (S is '0'), the output Q is SET to '1'. When only R is asserted (R is '0'), the output Q is RESET to '0'. When neither S and R are asserted, the output holds its previous value.

Figure 1. SR-Latch NAND cell.

SR-Latch is a kind of bi-stable circuit. However, due to propagation delay of NAND gate, it is possible to drive the circuit into metastable state, where the output is oscillating between 0 and 1. The metastable state will be triggered when neither the set operation nor the reset operation propagates through the whole cell before the cell changes to the hold state.

Step 1: Implement the Circuit in Verilog^®

Assume the NAND gates in SR-Latch have a delay of 1 ns. The Verilog file for the SR-Latch looks like follows:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

`timescale 1ns / 1ps module sr_latch(     input S,     input R,     output Q,     output Qn     );   wire Q_int, Qn_int;   assign #1 Q_int = ~(S & Qn_int); assign #1 Qn_int = ~(R & Q_int); assign Q = Q_int; assign Qn = Qn_int;   endmodule

Step 2: Create the Test Bench and Simulate the Circuit

For the purpose of demonstrating the functionality of SR-Latch, we consider the following input simulus:

• De-assert both inputs at the start of the simulation.
• At 100 ns, asset S.
• At 200 ns, de-assert S.
• At 300 ns, assert R.
• At 400 ns, de-assert R.
• At 500 ns, assert both inputs.
• At 600 ns, de-assert both inputs.
• At 700 ns, assert both inputs.

The codes in the test bench looks as follows:

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

initial begin     // Initialize Inputs     S = 1;     R = 1;           // Add stimulus here     #100 S = 0;     #100 S = 1;     #100 R = 0;     #100 R = 1;     #100 S = 0;          R = 0;     #100 S = 1;          R = 1;     #100 S = 0;          R = 0;     #100 ; end

Figure 2 below shows the simulated waveform of the circuit; at 300 ns, Reset signal is asserted. From the zoomed-in graph on the left, it takes 2 ns for Reset operation to propagate through the NAND cell. At 600 ns, both S and R toggles from 0 to 1, resulting in a change between an unfinished SET/RESET operation directly to hold state, which finally triggers an astable state (usually referred as meta-stability).

Figure 2. SR-Latch simulation waveform.

Screenshot above is from Xilinx ISim running on Microsoft Windows 7. Altered to enhance visual understanding.

Test Your Knowledge!

Now that you've completed this project, try these modifications:

1. Implement an SR-Latch using NOR Cell and simulate the NOR cell and see if you get a similar waveform as in Step 2.
2. Simulate the following input sequence on both a NAND cell and a NOR cell. Complete the following table by placing the correct letter in the output column:
   1. set operation
   2. reset operation
   3. confounded outputs (both outputs at the same voltage)
   4. storing a value in memory
   5. a metastable state

   Time	SET	RESET	NAND Cell	NOR Cell
   100 ns	1￫0	1￫1
   200 ns	0￫1	1￫0
   300 ns	1￫1	0￫1
   400 ns	1￫0	1￫0
   500 ns	0￫1	0￫1
   600 ns	1￫0	1￫0
   700 ns	0￫0	0￫1
   800 ns	0￫1	1￫0

3. Implement a D-Latch displayed in Fig. 3 below. Simulate it and try to drive it into a metastable state.

   

   Figure 3. D-Latch.

   HINT: An SR-Latch is driven into metastability by issuing a store operation before a set or reset operation is finished. Similarly, the D-Latch can be driven into stability by issuing a latching operation before the new data is updated to the D-Latch.

Challenge Problem

• If you are confident in your ability to implement and simulate the basic NAND cell of an SR-Latch, go ahead and try out the design challenge problem below for some extra practice!
• Design Problem 1.

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