HBLbits_Verilog Basic_Tb/tff

HBLbits_Verilog Basic_Tb/tff 

You are given a T flip-flop module with the following declaration:

module tff (
    input clk,
    input reset,   // active-high synchronous reset
    input t,       // toggle
    output q
);

Write a testbench that instantiates one tff and will reset the T flip-flop then toggle it to the "1" state.

`timescale 1ps / 1ps

    reg clk;
    reg reset;
    reg t;
    wire q;
    
tff dut(
        .clk(clk),
    .reset(reset),  // active-high synchronous reset
        .t(t),        // toggle
        .q(q)
);
    
  initial begin
        clk=1'b0;
        forever
        #5 clk=~clk;
    end
    
    initial begin
        reset = 1'b0;
        #3;
        reset = 1'b1;
        #10;
        reset = 1'b0;   
    end
    
    always@(posedge clk)begin
        if(reset)begin
            t <= 1'b0;
        end
        else begin
            t <= 1'b1;
        end
    end
 
endmodule

module top_module ();