HBLbits_Verilog Basic_Exams/m2014 q6b

HBLbits_Verilog Basic_Exams/m2014 q6b 

Consider the state machine shown below, which has one input w and one output z.

Assume that you wish to implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ... , 101 for states A, B, ... , F, respectively. Show a state-assigned table for this FSM. Derive a next-state expression for the flip-flop y[2].

Implement just the next-state logic for y[2]. (This is much more a FSM question than a Verilog coding question. Oh well.)

y[3:1]   ,   y[2]是中間bit

module top_module (
    input [3:1] y,
    input w,
    output Y2);
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101;
    assign Y2 = (y==B) || (y==F) || (y==C && w) || (y==E && w);
endmodule