HBLbits_Verilog Basic_Exams/2014 q3bfsm

HBLbits_Verilog Basic_Exams/2014 q3bfsm 

Given the state-assigned table shown below, implement the finite-state machine. Reset should reset the FSM to state 000.

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input x,
    output z
);
    parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100; 
    reg[2:0] current_state, next_state;
    
    always@(posedge clk)begin
        if(reset)begin
            current_state <= A;
        end
        else begin
            current_state <= next_state;
        end
    end
 
    always@(*)begin
        case(current_state)
            A: next_state = x?B:A;
            B: next_state = x?E:B;
            C: next_state = x?B:C;
            D: next_state = x?C:B;
            E: next_state = x?E:D;
            default: next_state = A;
        endcase
    end
    assign z= (current_state==D | current_state==E);
endmodule