HBLbits_Verilog Basic_Sim/circuit2

HBLbits_Verilog Basic_Sim/circuit2 

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//
//y = A'B'C'D' + A'B'CD + A'BC'D + A'BCD' + AB'C'D + AB'CD' + ABC'D' + ABCD
    assign q = (~a & ~b & ~c & ~d) | (~a & ~b & c & d)  |
        (~a &  b & ~c &  d) | (~a &  b & c & ~d) |
        ( a &  ~b & ~c &  d) | ( a &  ~b & c & ~d) |
        ( a &  b & ~c & ~d) | ( a &  b & c &  d);
   
endmodule