HBLbits_Verilog Basic_Exams/m2014 q6c

HBLbits_Verilog Basic_Exams/m2014 q6c 

Consider the state machine shown below, which has one input w and one output z.

For this part, assume that a one-hot code is used with the state assignment 'y[6:1] = 000001, 000010, 000100, 001000, 010000, 100000 for states A, B,..., F, respectively.

Write a logic expression for the next-state signals Y2 and Y4. (Derive the logic equations by inspection assuming a one-hot encoding. The testbench will test with non-one hot inputs to make sure you're not trying to do something more complicated).

module top_module (
    input [6:1] y,
    input w,
    output Y2,
    output Y4);
    parameter A=6'b000001,B=6'b000010,C=6'b000100;
    parameter D=6'b001000,E=6'b010000,F=6'b100000;
    assign Y2 = y[1] && ~w;
    assign Y4 = (y[2] | y[3] | y[5] | y[6]) && w;
endmodule