HBLbits_Verilog Basic_Sim/circuit8

 HBLbits_Verilog Basic_Sim/circuit8

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    output p,
    output q );
  always@(*)begin
        if(clock)begin
        p = a;
        end
    end
    
    always@(negedge clock)begin
        q <= p;
    end
endmodule

    input clock,