HBLbits_Verilog Basic_Sim/circuit5

HBLbits_Verilog Basic_Sim/circuit5 

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );
    //00 01 10 11 -->b , e ,a, d  c:sel
    always @(*) begin
        case (c)
            0: q=b;
            1: q=e;
            2: q=a;
            3: q=d;
            default: q=4'hf;
        endcase
    end

endmodule

    input [3:0] a,