HBLbits_Verilog Basic_Exams/m2014 q6

HBLbits_Verilog Basic_Exams/m2014 q6

 Consider the state machine shown below, which has one input w and one output z.

Implement the state machine. (This part wasn't on the midterm, but coding up FSMs is good practice).

module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
parameter A=3'b000,B=3'b001,C=3'b010,D=3'b011,E=3'b100,F=3'b101; 
    reg[2:0] current_state, next_state;
    
    always@(posedge clk)begin
        if(reset)begin
            current_state <= A;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            A: next_state = w?A:B;
            B: next_state = w?D:C;
            C: next_state = w?D:E;
            D: next_state = w?A:F;
            E: next_state = w?D:E;
            F: next_state = w?D:C;
            default: next_state = A;
        endcase
    end
  
    assign z = (current_state == E || current_state == F);
    
endmodule