HBLbits_Verilog Basic_Sim/circuit9

HBLbits_Verilog Basic_Sim/circuit9

This is a sequential circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

module top_module (
    input a,
    output reg [3:0] q );
    
    always@(posedge clk)begin
        if(a)begin
            q <= 4'd4;
        end
        else if(q == 4'd6)begin
            q <= 4'd0;
        end
        else begin
            q <= q + 1'b1;
        end
    end
 endmodule

    input clk,